Since semiconductor devices including integrated circuits (IC) operate at increasingly higher frequencies and data rates and at lower voltages, the production of noise in the power and ground (return) lines and the need to supply sufficient current to accommodate faster circuit switching become an increasingly important problem. In order to provide low noise and stable power to the IC, low impedance in the power distribution system is required. In conventional circuits, impedance is reduced by the use of additional surface mount capacitors interconnected in parallel. The higher operating frequencies (higher IC switching speeds) mean that voltage response times to the IC must be faster. Lower operating voltages require that allowable voltage variations (ripple) and noise become smaller. For example, as a microprocessor IC switches and begins an operation, it calls for power to support the switching circuits. If the response time of the voltage supply is too slow, the microprocessor will experience a voltage drop or power droop that will exceed the allowable ripple voltage and noise margin; the IC will malfunction. Additionally, as the IC powers up, a slow response time will result in power overshoot. Power droop and overshoot must be controlled within allowable limits by the use of capacitors that are close enough to the IC to provide or absorb power within the appropriate response time.
Capacitors for impedance reduction and minimizing power droop or dampening overshoot are generally placed as close to the IC as possible to improve circuit performance. Conventional designs for capacitor placement mount capacitors on the surface of a printed wiring board (PWB) clustered around the IC. Large value capacitors are placed near the power supply, mid-range value capacitors at locations between the IC and the power supply, and small value capacitors very near the IC. This distribution of capacitors is designed to reduce voltage response time as power moves from the power supply to the IC.
FIG. 1 is a schematic for a typical placement of capacitors. Shown is a power supply, an IC and the capacitors 4, 6, 8, which represent high value, mid-range value and small value capacitors, respectively, used for impedance reduction and minimizing power droop and dampening overshoot as described above.
FIG. 2 is a representative section view in front elevation showing the connections of Surface Mount Technology (SMT) capacitors 50 and 60 and IC device 40 to the power and ground planes in the substrate of the PWB. IC device 40 is connected to lands 41 by solder filets 44. Lands 41 are connected to plated-through hole via pads 82 of vias 90 and 100 by circuit lines 72 and 73. Via 90 is electrically connected to conductor plane 120 and via 100 is connected to conductor plane 122. Conductor planes 120 and 122 are connected one to the power or voltage side of the power supply and the other to the ground or return side of the power supply. Small value capacitors 50 and 60 are similarly electrically connected to vias and conductor planes 120 and 122 in such a way that they are electrically connected to IC device 40 in parallel. In the case of IC devices placed on modules, interposers, or packages, the large and medium value capacitors may reside on the printed wiring mother board to which the modules, interposers, or packages are attached.
A large number of capacitors, interconnected in parallel, is often needed to reduce power system impedance. This requires complex electrical routing, which leads to increased circuit loop inductance. In turn this increases impedance, constraining current flow, thereby reducing the beneficial effects of surface mounted capacitors. As frequencies increase and operating voltages continue to drop, increased power must be supplied at faster rates requiring increasingly lower inductance and impedance levels.
Considerable effort has been expended to minimize impedance. U.S. Pat. No. 5,161,086 to Howard, et al., provides one approach to minimizing impedance and “noise”. Howard, et al. discloses a capacitive printed circuit board with a capacitor laminate (planar capacitor) placed within the multiple layers of the laminated board with a large number of devices such as integrated circuits being mounted or formed on the board and operatively coupled with the capacitor laminate (or multiple capacitor laminates) to provide a capacitive function employing borrowed or shared capacitance. However, such an approach to capacitor placement does not provide for high capacitance and does not necessarily improve voltage response. Improved voltage response requires that the capacitor be placed closer to the IC. Moreover, simply placing the capacitor laminate closer to the IC is not a satisfactory technical solution to provide high capacitance because the total capacitance available may be insufficient.
U.S. Pat. No. 6,611,419 to Chakravorty discloses an alternate approach to embedding capacitors to reduce switching noise. The power supply terminals of an integrated circuit die can be coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic substrate.
Accordingly, the present inventors desired to provide a method of designing and making a power core that allows for impedance reduction combined with improved voltage response to accommodate higher IC switching speeds. The present invention provides such a device and method of making such a device.